Eliyan
Eliyan develops high-speed chiplet interconnect technologies that break through the I/O and memory walls limiting AI and high-performance computing performance. Its NuLink™ PHY IP cores and NuGear™ chiplets enable die-to-die, chip-to-chip, and die-to-memory connections with up to four times the bandwidth and twice the power efficiency of alternative solutions using standard or advanced packaging.
- Semiconductor
- Hardware
- Artificial Intelligence
Funding
Raised to date
$140MRaised to date based on public sources. This may differ from the amount the company actually raised and is based only on what is publicly available on the internet.
across 3 rounds
+3$40M · Strategic
Announced Aug 2024
Disclosed cumulative: $140M
Founders
Product
Problem
Chiplet-based systems face critical performance limits due to the "memory wall" and "I/O wall," where interconnect bandwidth and power efficiency constrain overall system performance, especially in AI applications requiring high data throughput. Over the past 20 years, compute capability has increased 100,000x while DRAM bandwidth and I/O bandwidth have only increased 30x, limiting HPC/AI system performance. Traditional interconnect approaches struggle to support the increasing size, complexity, and power demands of these multi-die systems.
Solution
Eliyan provides advanced chiplet interconnect technologies that enable efficient communication across compute, memory, and electro-optical domains in AI and HPC systems. Its NuLink™ PHY technology delivers high-bandwidth, low-power die-to-die and chip-to-chip connections using either standard organic substrates or advanced packaging, achieving up to 4x the bandwidth and 2x the power efficiency of competing solutions. The NuLink™-XS family extends reach for chip-to-chip connections across PCB, while the NuLink™-XD 224G PAM4 SerDes enables low-power electro-optical modules for AI scale-up networks. These technologies support industry standards (UCIe, BoW) as well as proprietary methods like UMI™ and simultaneous bidirectional (SBD) signaling.
Target Audience
Primary customers are hyperscalers, AI accelerator developers, memory suppliers, and semiconductor manufacturers building multi-die AI and HPC systems that require high-bandwidth, power-efficient interconnect solutions. The technology also serves system designers integrating chiplets through standard packaging to reduce cost and time-to-market.
Features
- NuLink™ PHY IP cores for die-to-die connections on standard packaging (100-130um bump pitch) achieving up to 64 Gbps per lane at 4.1 Tbps/mm² area bandwidth
- NuLink-AP PHY IP for advanced packaging (silicon interposer/bridge, 40-55um bump pitch) delivering up to 21.1 Tbps/mm² beachfront bandwidth with simultaneous bidirectional capability
- NuLink-XS chip-to-chip PHY IP that reaches 100mm on PCB with data rates up to 64 Gbps per lane at significantly lower power than 112G/224G SerDes
- UMI™ (Universal Memory Interface) for bandwidth-efficient die-to-memory connections that reduces die area needed for memory interfaces
- NuGear chiplet products for memory and I/O subsystems that break through the memory wall in HPC/AI systems
- Support for industry standards including UCIe, BoW, and the Arm Foundation Chiplet System Architecture (FCSA), enabling open chiplet interoperability