Funding
Funding not disclosed
Founders
Product
Problem
IC design projects often face challenges in meeting deadlines due to design bugs, performance revisions, or specification changes discovered late in the design cycle. Reworking the entire design is time-consuming and costly, especially when changes are needed after layout and routing.
Solution
Easy-Logic Technology provides the EasyECO solution, an electronic design automation (EDA) tool that streamlines functional engineering change order (ECO) implementation. EasyECO automates the modification of gate-level netlists based on RTL code changes, ensuring consistency between the revised RTL and the implemented design. The tool uses a patented algorithm to identify optimal ECO points and generate minimal patch logic, preserving the existing design netlist as much as possible. EasyECO supports patch logic creation, metal-only post-layout ECO, and scan chain fixing, integrating seamlessly into existing ASIC design flows.
Target Audience
The primary customers are ASIC design companies seeking to reduce design cycle time and costs by efficiently implementing functional ECOs, including design teams working on panel driver ICs and other complex integrated circuits.
Features
- Automatic netlist modification based on RTL code changes
- Patented algorithm for identifying optimal ECO points
- Minimal patch logic generation to preserve design integrity
- Support for patch logic creation, metal-only post-layout ECO, and scan chain fixing
- Physical-aware solution for optimized ECO patches with minimal metal layer changes
- Automatic revision of scan chain netlist to accommodate updated logic functions
- Compatibility with standard input/output formats for easy integration with existing design flows
- Template-based scripts for various application scenarios
- Support for designs up to 5 million instances
- Optimized for advanced process technologies (10nm and below)