DragonX Systems
DragonX Systems provides an agentic semiconductor design automation platform that uses GPU-native physics solvers and autonomous AI agents to compress physical closure time by 7–10×. The Accelane engine integrates CUDA-accelerated logic synthesis, electrostatic analytical placement, routing, and STA signoff into a single pipeline, validated on TSMC 28nm with 100M+ gate hierarchical capacity.
- Semiconductor
- AI Agents
- Artificial Intelligence
- Software Only
Funding
Founders
Founder details are not available yet.
Product
Problem
Traditional semiconductor physical design flows rely on CPU-bound tools and sequential, human-in-the-loop iterations, making full-chip closure at advanced nodes a multi-week or multi-month process. Congestion, timing violations, and DRC errors compound across 100M+ gate hierarchies, delaying time-to-market for complex SoCs.
Solution
DragonX Systems delivers an agentic semiconductor design automation platform that fuses AI-driven engineering with GPU-native physics solvers to compress physical closure time by 7–10×. Autonomous AI agents collaborate with hardware architects, maintaining a living model of the SoC design with foundry DRC constraints, timing graphs, and physics encoded into memory. Engineers can instruct the system to hit timing targets or resolve congestion, and receive verified solutions in seconds. The integrated toolchain bridges high-level system-on-chip exploration directly to GPU-accelerated GDSII physical closure, with traceability back to placement and routing engines. The system combines CUDA-accelerated logic synthesis, electrostatic analytical placement, global/detailed routing, and STA timing/power signoff in a single automated pipeline.
Target Audience
Primary customers are hardware architects, physical design engineers, and SoC design teams at semiconductor companies and advanced-node chip developers requiring accelerated physical closure for complex, large-scale designs.
Features
- GPU-native physics solvers for electrostatic analytical placement with HPWL optimization and zero cell overlap
- Autonomous AI agents that interpret design goals (e.g., timing target on a 1.8 GHz tile) and return verified solutions in seconds
- Full-chip hierarchical capacity supporting 100M+ gate designs
- Integrated CUDA Yosys logic synthesis and analytical routing engines with DRC-short-free global/detailed routing
- STA timing & power signoff with WNS reporting, achieving zero-violation timing and DRC closure
- TSMC 28nm HPC+ PDK-ready flow with benchmarked 7.8× faster closure speeds
- Four tightly coupled GPU execution stages (synthesis, placement, routing, signoff) running on shared memory without file serialization bottlenecks
- Auto-healing ECO generators that rank buffer insertions and wire spacing patches without manual script intervention