DeepGate offers a web‑based drag‑and‑drop platform that automates profiling, compilation, and compression of trained machine‑learning models for microcontroller units (MCUs). The service produces optimized binaries and an SDK with custom inference kernels, reducing RAM, flash usage, and latency to enable efficient on‑device AI integration.
Funding
Funding not disclosed
Founders
Product
Problem
Deploying machine‑learning models on microcontroller units (MCUs) is constrained by limited RAM, flash storage, and processing power, making manual optimization labor‑intensive and error‑prone. Engineers often must rewrite or heavily prune models to meet these tight resource budgets, which slows time‑to‑market for edge AI products.
Solution
DeepGate offers a web‑based, drag‑and‑drop platform that automates the end‑to‑end workflow for MCU‑targeted AI. Users upload a trained model, which the system profiles across a catalog of supported MCUs to identify the best fit. A purpose‑built compiler generates optimized binaries, while an automated compression engine reduces memory and flash footprints without sacrificing accuracy. The resulting artifacts are delivered through an SDK that includes custom inference kernels and logic‑neural‑network layers, enabling developers to integrate high‑performance AI into firmware with minimal code changes. The platform also provides performance benchmarks and versioned builds to streamline validation and deployment.
Target Audience
The primary customers are product and engineering teams building AI‑enabled IoT devices, as well as silicon and platform partners seeking to embed efficient on‑device inference into their offerings.
Features
- Visual drag‑and‑drop interface for model upload, profiling, and download, eliminating manual build steps
- Multi‑MCU profiling engine that evaluates model compatibility across vendors and core architectures (e.g., Cortex‑M7)
- DeepGate compiler delivering up to 53 % faster inference, 27 % lower RAM usage, and 78 % reduced flash compared with TensorFlow Lite for Microcontrollers on MLPerf Tiny benchmarks
- Automated agentic compression pipeline that achieves up to 30 % faster inference and 27 % RAM savings while preserving model accuracy
- SDK with custom inference kernels and logic‑neural‑network layers, offering up to 69× faster inference and dramatically lower memory footprints versus standard libraries
- Export of ready‑to‑flash binary files and header assets for seamless integration into existing firmware build systems
- Cloud‑hosted benchmarking dashboard that records latency, memory, and power metrics for each target device