DashTechIC provides a domain‑adaptive processor built on the DASH SoC framework that can re‑configure accelerator pipelines on‑the‑fly, delivering ASIC‑level performance while retaining the flexibility of programmable devices. The platform integrates proprietary inter‑chip communication to minimize latency and bandwidth constraints, enabling rapid application switching for AI inference, signal processing, and edge computing workloads.
Funding
Funding not disclosed
Founders
Product
Problem
Designers of high‑performance hardware face a trade‑off between the flexibility of programmable devices (e.g., FPGAs) and the efficiency of fixed ASICs, leading to long re‑configuration times, sub‑optimal performance, and bottlenecks in inter‑chip data transfer.
Solution
DashTechIC offers a domain‑adaptive processor built on the DASH SoC framework that can re‑configure accelerator behavior on‑the‑fly, enabling rapid switching between applications without the overhead of traditional FPGA workflows. The architecture delivers ASIC‑level throughput while retaining out‑of‑the‑box adaptability for a broad set of workloads. By integrating proprietary inter‑chip communication techniques, the platform eliminates latency and bandwidth constraints that limit other high‑performance processors. This combination allows system designers to achieve both high efficiency and flexibility in a single silicon solution, reducing time‑to‑market and overall system cost.
Target Audience
Primary customers are semiconductor OEMs, ASIC designers, and system integrators that require high‑performance, reconfigurable compute solutions for applications such as AI inference, signal processing, and edge computing.
Features
- Domain‑adaptive processor that dynamically re‑configures accelerator pipelines for instant application switching
- DASH SoC framework providing ASIC‑grade performance with programmable flexibility across diverse workloads
- Integrated inter‑chip data transfer architecture that minimizes latency and maximizes bandwidth
- Unified design flow that consolidates hardware development, reducing reliance on separate FPGA and ASIC toolchains
- Scalable architecture suitable for integration into custom ASICs, system‑on‑chip designs, and heterogeneous compute platforms