Daidalos provides a plug‑and‑play AI accelerator IP that can be integrated directly into custom System‑on‑Chip designs or implemented on FPGA platforms. The architecture abstracts hardware complexity with an automated mapping workflow, delivering high performance‑per‑watt edge AI inference while reducing design time and power consumption. It targets semiconductor firms, robotics manufacturers, and aerospace companies needing efficient, low‑latency AI processing in their products.
Funding
Funding not disclosed
Founders
Product
Problem
Designing and integrating AI acceleration hardware into semiconductor products, robotics platforms, or space systems often requires extensive custom engineering, long development cycles, and high power consumption, limiting time‑to‑market and efficiency.
Solution
Daidalos offers a plug‑and‑play AI accelerator architecture that can be directly integrated into custom System‑on‑Chips (SoCs) or implemented on FPGA platforms. The solution abstracts the underlying hardware complexity, providing a standardized mapping workflow and compatibility layer that shortens integration effort and reduces architectural overhead. By optimizing the balance between computational speed and energy use, the accelerator enables real‑world edge AI deployments in demanding verticals such as robotics, aerospace, and other high‑value applications. Customers can thus accelerate AI workloads with lower power budgets while maintaining control over the hardware stack.
Target Audience
Primary customers are semiconductor companies developing custom SoCs, robotics manufacturers, and aerospace or space technology firms that require efficient, low‑latency AI processing in their hardware products.
Features
- Modular accelerator IP that can be instantiated in ASIC or FPGA designs with minimal code changes
- Automated mapping and integration workflow that reduces design‑time and verification effort
- Energy‑efficient compute units optimized for edge AI inference, delivering high performance per watt
- Compatibility layer supporting common AI frameworks and model formats for seamless deployment
- Scalable architecture configurable for a range of performance targets, from low‑power embedded nodes to high‑throughput robotics controllers