CoolSem Technologies provides a patented wafer‑level carrier, WaLTIS®, that replaces the traditional silicon substrate to create a thermal pathway up to 15× more conductive while remaining dielectrically neutral. This reduces substrate thermal resistance, eliminates hotspots, and matches the die’s coefficient of thermal expansion, improving performance and reliability of high‑power RF and 5G/6G antenna systems without requiring layout changes.
Funding
Funding not disclosed
Founders
Product
Problem
Semiconductor chips generate heat that must be removed to maintain performance and reliability, but traditional cooling methods address only package‑level heat removal while the dominant thermal resistance resides in the chip’s substrate. Additionally, temperature cycling causes mismatched material expansion, creating mechanical stress that degrades interfaces and further impedes heat flow.
Solution
CoolSem Technologies tackles the substrate‑level bottleneck by replacing the conventional silicon substrate with a patented wafer‑level carrier that provides a thermal pathway up to 15 × more conductive. The WaLTIS® carrier conducts heat efficiently while matching the die’s coefficient of thermal expansion, eliminating hotspots and reducing mechanical stress. Because the carrier is dielectrically neutral, it integrates with existing device layouts and electrical isolation schemes without requiring redesign. This approach improves both performance and long‑term reliability of high‑power RF and 5G/6G antenna systems, enabling higher power density and sustained operation in demanding outdoor environments.
Target Audience
Primary customers are semiconductor manufacturers and RF system designers developing high‑power 5G/6G base‑station and antenna solutions that require advanced thermal management.
Features
- Patented WaLTIS® wafer‑level carrier that reduces thermal resistance by up to 15× compared to standard substrates
- Thermal conductivity comparable to metal while maintaining dielectric neutrality for seamless integration with existing designs
- Coefficient of thermal expansion matched to the active die, minimizing thermomechanical stress during temperature cycles
- No layout constraints; compatible with current device footprints and electrical isolation strategies
- Enables efficient heat removal for high‑power RF base stations and future 5G/6G antenna arrays