Codasip provides customizable RISC-V processor solutions that allow developers to tailor microarchitecture and instruction sets to meet specific performance, power, and area requirements. This enables technology innovators to create differentiated products while ensuring compliance with safety and cybersecurity standards.
Funding
$16.5M raised to dateRaised to date based on public sources. This may differ from the amount the company actually raised and is based only on what is publicly available on the internet.
Founders
Product
Problem
General-purpose processor cores often force compromises in performance, power consumption, and silicon area, especially when running specialized algorithms or workloads. Traditional processor design lacks the flexibility to fully optimize the instruction set architecture (ISA) and microarchitecture for specific application requirements, leading to inefficiencies.
Solution
Codasip provides customizable RISC-V processor IP and design automation tools that enable developers to tailor processor microarchitecture and ISA to meet specific application needs. The Codasip Studio EDA tool and CodAL processor description language facilitate the co-development of hardware and software, resulting in optimized performance, power, and area. This approach allows for the creation of application-specific processors that outperform general-purpose cores in targeted tasks, while maintaining RISC-V compliance and ensuring safety and cybersecurity standards. Codasip's solutions also support the integration of CHERI technology for enhanced memory protection and cyberattack prevention.
Target Audience
The primary target audience includes technology innovators and chip designers developing application-specific processors for markets such as automotive, embedded systems, and high-performance computing.
Features
- Customizable RISC-V processor cores that allow modification of both microarchitecture and ISA
- Codasip Studio EDA tool for processor design automation and customization
- CodAL processor description language for hardware/software co-development
- Support for application-specific instruction set extensions and custom instructions
- TÜV SÜD certified IP hardware development process according to ISO 26262 and ISO/SAE 21434
- Optional integration of CHERI technology for memory protection against cyberattacks
- Pre-verified options for core configuration and custom instruction creation