Co-founder & CEO
Profile summary: PhD in Computer Science at University of Illinois at Urbana-Champaign
ChipStack
ChipStack provides a suite of AI agents that automate key verification tasks early in the RTL design flow, including testbench generation, formal property creation, unit-level simulation, and UVM environment management. By leveraging large language models and domain‑specific knowledge, the platform reduces manual effort, shortens verification cycles, and integrates with existing EDA toolchains, helping semiconductor and ASIC/FPGA design teams accelerate verification and lower costs.
- Artificial Intelligence
- AI Agents
- Developer Tools
- Semiconductor
Updated 5 months ago
Funding
Raised to date
$7.1MRaised to date based on public sources. This may differ from the amount the company actually raised and is based only on what is publicly available on the internet.
across 1 round
DVRoundDateAmountValuationInvestors
Founders
Product
Problem
Chip design verification consumes more than 60% of development time, with frequent handoffs between design and verification teams causing schedule delays, higher costs, and a shortage of verification expertise.
Solution
ChipStack offers a suite of agentic AI verification agents that integrate early in the RTL design flow to automate and accelerate verification tasks. Its Mental Model, Formal, Unit Simulation, and UVM AI agents generate testbenches, create formal properties, run unit-level simulations, and manage UVM environments with minimal human intervention. By leveraging large language models and domain-specific knowledge, the platform reduces manual effort, shortens verification cycles, and enables engineers to focus on higher‑level design challenges. Results and artifacts are produced in standard formats compatible with existing EDA toolchains, facilitating seamless adoption within current workflows.
Target Audience
Primary customers are semiconductor companies, ASIC/FPGA design houses, and verification teams that need to reduce verification time and reliance on scarce expertise.
Features
- AI-driven generation of RTL testbenches and stimulus vectors
- Automated formal property creation and verification using a Formal AI Agent
- Unit-level simulation orchestration via a Unit Simulation AI Agent
- UVM environment setup and management through a dedicated UVM AI Agent
- Integration hooks for common EDA tools and design repositories
- Continuous learning from verification feedback to improve future agent performance