Bronco provides an AI‑driven verification platform that automates key digital verification (DV) tasks for ASIC and FPGA design teams. Its specialized agents generate UVM testbench code up to ten times faster and parse large specifications to produce comprehensive verification plans, reducing manual effort and accelerating bug detection. The platform supports on‑premises and BYOA deployment, ensuring IP security while integrating with existing verification flows.
Funding
$500K raised to dateRaised to date based on public sources. This may differ from the amount the company actually raised and is based only on what is publicly available on the internet.
Founders
Product
Problem
As chip designs become increasingly complex and development timelines shorten, verification teams struggle to keep up, leading to longer backlogs, missed bugs, and lower first‑time silicon success rates.
Solution
Bronco provides an AI‑driven verification platform that automates key DV tasks, enabling design teams to accelerate bug detection and reduce manual effort. Specialized agents generate UVM testbench code, including novel stimulus and checkers, up to ten times faster than traditional methods. The platform also parses large specification documents, enriches them, and produces comprehensive verification plans, ensuring coverage gaps are identified early. All capabilities are delivered through a single, secure environment that supports on‑premises deployment and bring‑your‑own‑AI models, protecting intellectual property while integrating with existing design flows.
Target Audience
Bronco targets ASIC and FPGA verification teams in semiconductor companies and design houses that need to accelerate DV workflows and improve first‑silicon success rates.
Features
- Agentic code generation that automatically creates UVM stimulus and checker modules from design intent
- Automated specification analysis that extracts requirements and produces verification plans
- End‑to‑end platform covering the verification lifecycle from spec ingestion to sign‑off
- On‑premises and BYOA deployment options for full IP security and compliance
- Integration hooks for existing verification environments and toolchains
- Scalable AI models optimized for large, complex chip designs