Sehat Sutardja
Founder
Blue Cheetah Analog Design, Inc.
The startup develops silicon technology that enables engineers to customize designs and streamline the silicon fabrication process, significantly reducing time-to-silicon for new generations of products. By codifying design methodologies, the technology minimizes risks associated with silicon engineering, allowing for faster innovation cycles.
- Hardware
- Semiconductor
Updated 2 days ago
Funding
Raised to date
$31.3MRaised to date based on public sources. This may differ from the amount the company actually raised and is based only on what is publicly available on the internet.
Funding rounds are not available yet.
Founders
Weili Dai
Founder
Product
Problem
The increasing complexity of chiplet designs and the need for high-bandwidth, low-power die-to-die communication pose significant challenges for engineers. Existing interconnect solutions often lack the customization and optimization required for specific applications, leading to increased development time and compromised performance.
Solution
Blue Cheetah provides customizable, standards-based chiplet interconnect IP solutions that address the challenges of die-to-die communication. Their BlueLynx™ IP, supporting UCIe and BoW standards, offers physical (PHY) and link layer interfaces tailored to individual chiplet needs. By enabling customization of packaging type, data rate, and I/O configuration, Blue Cheetah optimizes designs for area, power, and performance (PPA). Their executable generator technology further reduces development time and risk, ensuring first-pass silicon success.
Target Audience
The primary target audience includes chipmakers in the AI, high-performance computing, and mobile markets who require customizable, high-bandwidth die-to-die interconnect solutions for chiplet architectures.
Features
- BlueLynx™ IP supports UCIe v1.1 FLIT Data Interface (FDI) and Open Compute Project (OCP) Bunch of Wires (BoW) standards.
- Customizable die-to-die solutions with options for packaging type, data rate, and I/O configuration.
- Industry-leading PPA and bandwidth density, achieving 40+ Gbps/line and 15+ Tbps/mm.
- Support for 2D, advanced 2.5D, and 3D packaging applications.
- Available in 7 nodes across multiple foundries (16nm, 12nm, 7nm, 6nm, 5nm, 4nm, 3nm and below).
- PHY supports data rates from 2-40+ Gb/s with low latency of < 2 ns PHY-to-PHY.
- Integrated microcontroller and PLL, with built-in self-test (BIST) and diagnostic logic.
- Compiler-like development process produces industry-standard design collateral.