Sailesh Kumar
CEO
Baya Systems
10/10Traction
Baya Systems develops customizable, software-driven System IP solutions for chiplet-based semiconductor systems, enabling efficient data movement and high-performance computing. Their technology addresses the complexity and cost of delivering scalable, modular architectures by providing a unified fabric that supports advanced cache coherency and optimized throughput for diverse applications.
- Artificial Intelligence
- Developer Tools
- Enterprise Software
- Semiconductor
Updated 5 months ago
Funding
Raised to date
$47MRaised to date based on public sources. This may differ from the amount the company actually raised and is based only on what is publicly available on the internet.
MatrixNo round attributed
- matrix.vc (opens in a new tab)investor website
Funding rounds are not available yet.
Founders
Product
Problem
The increasing complexity and modularity of chiplet-based semiconductor systems present challenges in efficiently managing data movement and ensuring high-performance computing. Delivering scalable architectures while controlling costs and complexity requires a unified approach to support advanced cache coherency and optimized throughput across diverse applications.
Solution
Baya Systems offers customizable, software-driven System IP solutions designed to streamline data movement and enhance performance in chiplet-based systems. Their technology provides a unified fabric that addresses the challenges of delivering scalable, modular architectures. By separating transport from protocol layers, Baya Systems minimizes wiring and logic, creating a Network on Chip (NoC) that supports coherent, non-coherent, and custom protocols. This approach enables efficient data throughput, reduces risk through software-driven design, and allows for algorithmic optimization of workloads.
Target Audience
The primary target audience includes designers and developers of complex, intelligent computing systems in datacenters, infrastructure, AI acceleration, automotive, and IoT markets.
Features
- High-performance transport fabric delivering up to 4TB/s throughput per cluster, scaling to multiple PB/s for multi-chiplet AI applications.
- Flexible Network on Chip (NoC) customizable to any topology and extensible to custom protocols for AI, QoS, and debugging.
- Unified fabric supporting coherent (CHI, CXL), non-coherent (AMBA 5), and custom protocols.
- Software-driven development ensuring correct-by-construction NoC, validated through traditional and formal methods.
- Modular components for improved flexibility and faster design delivery, utilizing physical design-aware tiling.
- WeaverPro software components for architectural exploration, analysis, configuration, and optimization, featuring a built-in simulator and SystemC/Python APIs.
- WeaveIP portfolio built on a common transport, optimized for minimal power and silicon footprint.
- Supports multi-level cache coherency, multicast capability for AI acceleration, and features for Reliability, Availability, and Serviceability (RAS).