Aule Technologies offers Zyphar, a generative AI engine that automates VLSI physical chip design from floorplanning through to GDSII output. By leveraging a purpose-built model with DRC/LVS-aware inference and multi‑foundry PDK support, Zyphar can reduce tape‑out cycles from weeks to days, enabling engineers to generate high‑fidelity chip layouts quickly.
Funding
Funding not disclosed
Founders
Product
Problem
Designing the physical layout of VLSI chips requires extensive manual effort across floorplanning, placement, routing, and final GDSII generation, often taking weeks and risking rule violations that can delay tapeout.
Solution
Zyphar, Aule Technologies’ generative AI engine, automates the entire physical design flow from netlist to GDSII output. The model produces layout data that is DRC and LVS aware, ensuring compliance with design rules across multiple foundry PDKs. By generating high‑fidelity GDSII files in a matter of days, Zyphar shortens tapeout cycles and reduces the need for iterative manual fixes. Engineers can submit a netlist through a web interface and receive a ready‑to‑tapeout layout, accelerating production while maintaining quality. The platform is offered as a public preview with options for enterprise PDK access, tapeout support, and custom deployments.
Target Audience
Primary customers are VLSI design teams at semiconductor companies and fabless startups that need rapid, rule‑compliant physical design for tapeout.
Features
- End‑to‑end generative pipeline that creates floorplan, placement, routing, and final GDSII from a netlist
- Built‑in DRC and LVS awareness to produce rule‑compliant layouts automatically
- Support for multiple foundry process design kits (PDKs) enabling cross‑foundry designs
- High‑fidelity GDSII output suitable for immediate tapeout without extensive post‑processing
- Web‑based submission portal with free account for quick netlist upload and result retrieval