Arteris provides semiconductor system IP and SoC integration automation tools to accelerate the development of advanced systems-on-chip. Their silicon-proven Network-on-Chip (NoC) interconnect IP and automation software help companies achieve higher performance, reduce power consumption, and shorten time-to-market.
Funding
$5.4M raised to dateRaised to date based on public sources. This may differ from the amount the company actually raised and is based only on what is publicly available on the internet.
Founders
Product
Problem
Developing complex systems-on-chip (SoCs) involves significant challenges in managing interconnectivity, ensuring performance, and optimizing power consumption. Traditional approaches to SoC integration often lead to extended development cycles, increased design complexity, and difficulties in achieving optimal power, performance, and area (PPA) targets.
Solution
Arteris provides a comprehensive suite of semiconductor system IP and SoC integration automation tools designed to accelerate the development of advanced SoCs. Their offerings include silicon-proven Network-on-Chip (NoC) interconnect IP and automation software that address the core challenges of SoC design. By leveraging Arteris' technology, semiconductor companies can achieve higher product performance, reduce power consumption, and shorten time-to-market. The company's solutions are engineered to manage complexity, de-risk projects, and enhance engineering productivity, enabling the creation of more efficient and powerful silicon devices.
Target Audience
Arteris targets semiconductor companies and technology firms involved in the design and development of complex systems-on-chip, including those focused on AI, automotive, communications, and enterprise computing markets.
Features
- **FlexGen Smart NoC IP:** AI-driven interconnect IP that optimizes wire length, topology, and latency for improved performance and efficiency.
- **Ncore Cache Coherent Interconnect IP:** High-bandwidth, low-latency NoC IP supporting heterogeneous coherency and multi-die configurations, with ISO 26262 ASIL D readiness.
- **FlexNoC Interconnect IP:** Physically aware NoC IP that assists with timing closure, reduces area and power, and supports flexible topologies and advanced QoS.
- **CodaCache Last-Level Cache IP:** Configurable last-level cache IP designed to resolve critical SoC design challenges related to performance optimization, data access, and power efficiency.
- **Magillem Packaging:** Automation tool for packaging IP into IP-XACT files, facilitating integration, configuration, and validation of IP blocks.
- **Magillem Connectivity:** SoC integration automation software that streamlines IP deployment and automates SoC assembly for faster, error-free integration.
- **Magillem Registers:** Hardware/Software Interface (HSI) automation tool for managing registers, ensuring consistency across hardware and software development, and generating documentation.
- **CSRCompiler:** A complete register design solution for HSI verification and documentation, supporting various input formats and generating multiple outputs.