AICO develops SPLEAT, a neuromorphic computing architecture designed for very-low-power AI applications. SPLEAT offers significant power and hardware resource savings compared to other AI accelerators, enabling powerful computer vision, voice analysis, and RF signal processing in battery-powered devices like satellites, drones, and wearables.
Funding
Funding not disclosed
Founders
Product
Problem
Many AI applications, especially those in battery-powered devices like satellites, drones, and wearables, are limited by the high power consumption and resource demands of traditional computing architectures. This restricts the deployment of advanced AI capabilities in edge computing scenarios where energy efficiency is paramount.
Solution
AICO Technology offers SPLEAT, a neuromorphic computing architecture designed to drastically reduce power consumption and hardware resource requirements for AI applications. SPLEAT enables the deployment of computer vision, voice analysis, and RF signal processing in power-constrained environments. The architecture achieves significant power and surface efficiency gains compared to conventional AI accelerators, making it suitable for integration into custom system-on-chip designs on both FPGA and ASIC platforms.
Target Audience
The primary target audience includes developers and manufacturers of battery-powered devices, such as satellites, drones, and wearables, seeking to implement AI functionalities with minimal energy footprint, as well as researchers and companies interested in neuromorphic computing.
Features
- Neuromorphic architecture optimized for ultra-low-power AI inference
- Demonstrated 10x improvement in power efficiency compared to traditional ASICs
- Demonstrated 10x improvement in surface efficiency compared to traditional ASICs
- Demonstrated 10x improvement in logic resource efficiency compared to traditional FPGAs
- FPGA devkit available for testing and exploration of SPLEAT capabilities
- Qualia SDK software for model deployment and SPLEAT configuration
- IP license available for deploying SPLEAT in custom FPGA or ASIC designs
- Sub-mW power consumption for keyword spotting on ASIC (22nm, simulated)
- Real-time object detection on FPGA with up to 2 million parameters, consuming 1.5W