AI Chips provides a full‑stack semiconductor service that designs, verifies, and fabricates custom ASIC and FPGA inference accelerators optimized for edge AI workloads. It handles architecture definition, RTL design, physical layout, DFT, and post‑silicon bring‑up across 28 nm to 3 nm nodes, enabling OEMs and system integrators to deploy low‑power, high‑throughput AI silicon for robotics, autonomous vehicles, 5G infrastructure, and industrial IoT.
Funding
Funding not disclosed
Founders
Product
Problem
Edge AI applications such as robotics, autonomous vehicles, and 5G infrastructure require inference accelerators that deliver high compute density while meeting strict size, weight, power, and cost (SWaP‑C) constraints. Conventional CPUs and GPUs are too power‑hungry and bulky for these edge deployments, leading to latency, thermal, and budget challenges.
Solution
AI Chips delivers a full‑stack semiconductor service that designs, verifies, and fabricates custom ASIC and FPGA accelerators optimized for machine‑learning inference at the edge. The company starts with architecture definition and specification tailoring for performance, power, and area (PPA) targets, then proceeds through RTL coding in Verilog/SystemVerilog, functional and formal verification, and physical layout using industry‑standard EDA tools. Design‑for‑test (DFT) features such as scan insertion and built‑in self‑test are integrated to ensure manufacturability and yield. Clients can prototype designs on FPGAs before tape‑out, and AI Chips supports tape‑out and post‑silicon bring‑up across advanced process nodes from 28 nm down to 3 nm. The service also includes mixed‑signal ASIC development, edge System‑on‑Chip (SoC) integration of CPU, GPU, NPU, and DSP cores, and secure data handling for AI workloads. By handling the entire semiconductor lifecycle, AI Chips enables customers to bring low‑power, high‑performance AI silicon to market faster and at lower volume cost.
Target Audience
Primary customers are OEMs and system integrators building edge AI hardware for robotics, autonomous vehicles, 5G base stations, drones, and industrial IoT devices that demand low‑power, high‑throughput inference accelerators.
Features
- Architecture & specification phase that optimizes speed, power, and area for target AI inference workloads
- RTL design and verification using Verilog/SystemVerilog with UVM‑based testbenches and coverage analysis
- Physical design (layout) with timing closure, power optimization, and multi‑patterning support for 28 nm–3 nm nodes
- Built‑in Design‑for‑Test (DFT) including scan chains, ATPG, and MBIST/LBIST for high yield and low debug cost
- FPGA prototyping flow for rapid validation before ASIC tape‑out
- Mixed‑signal ASIC integration enabling analog front‑ends alongside digital AI cores
- Edge SoC development that co‑integrates CPU, GPU, NPU, and DSP blocks with adaptive power management
- End‑to‑end tape‑out coordination and post‑silicon bring‑up support with characterization and debug services