Agile Analog provides a configurable, multi‑process analog IP platform (Composa™) that automatically generates custom data converters, power‑management blocks, and monitoring sensors for any foundry and technology node. The digitally wrapped, pre‑verified IP integrates directly into RTL flows, reducing design complexity, time‑to‑market, and the cost of custom analog development for ASIC and SoC teams.
Funding
$28.6M raised to dateRaised to date based on public sources. This may differ from the amount the company actually raised and is based only on what is publicly available on the internet.
IFounders
Product
Problem
Designing analog IP for ASICs and SoCs is time‑consuming, costly, and often tied to a specific foundry or process node, limiting flexibility and slowing product development cycles.
Solution
Agile Analog offers a configurable, multi‑process analog IP platform (Composa™) that automatically generates custom analog blocks—such as data converters, power‑management circuits, and on‑chip monitoring sensors—tailored to the customer’s chosen foundry and technology node. The IP is digitally wrapped and pre‑verified, enabling seamless integration into any SoC with minimal effort. Customers can select from a catalog of functional specifications and receive IP with varying levels of customization, from off‑the‑shelf to fully bespoke designs, delivered within weeks. This approach reduces design complexity, shortens time‑to‑market, and eliminates the need for extensive analog design expertise or costly custom development.
Target Audience
Primary customers are ASIC and SoC design teams in industries such as high‑performance computing, IoT, automotive, aerospace, and AI who need analog functionality integrated into their chips quickly and cost‑effectively.
Features
- Configurable analog IP generation across all major foundries and process nodes using the Composa methodology
- Wide portfolio covering high‑performance ADC/DACs, LDO regulators, bandgap references, and on‑chip temperature/voltage sensors
- Digitally wrapped, pre‑verified IP blocks that integrate directly into RTL flows with standard interfaces
- Flexible customization options: rapid (no customization), quick (partial), or agile (full) tailoring to meet specific performance targets
- Fast delivery timelines (as short as 4 weeks for standard parts) with optional deeper customization cycles
- Compatibility with standard design tools and verification environments, reducing integration effort