Abacus Semiconductor offers the Kloth Architecture™ compute platform, which adds scale‑out ports to each CPU and accelerator core for direct, high‑bandwidth inter‑processor communication and integrates an intelligent HRAM memory subsystem that removes traditional memory controllers. This design delivers significantly higher performance per watt and lower heat for AI, HPC, and database workloads while embedding built‑in cybersecurity for secure on‑premises and hybrid‑cloud deployments.
Funding
Funding not disclosed
Founders
Product
Problem
Current CPUs and GPGPUs are limited by interconnect and memory bandwidth constraints, creating bottlenecks that hinder scaling of high‑performance computing (HPC), AI training, and other compute‑intensive workloads. On‑premises data‑center operators also face higher total‑cost‑of‑ownership because legacy architectures are not optimized for instruction‑ and energy‑efficiency. These limitations reduce performance per watt and increase infrastructure and operating costs for AI and HPC clusters.
Solution
Abacus Semiconductor’s Kloth Architecture™ introduces a patented compute platform that adds a scale‑out port to each CPU and accelerator core, enabling direct, high‑bandwidth communication between processors, accelerators, and smart memories. The architecture incorporates Heterogeneous Random Access Memory (HRAM), which provides an intelligent, multi‑homed memory subsystem that eliminates the need for processor‑embedded memory controllers. Together with a Server‑on‑a‑Chip that integrates compute, virtualization, and memory support, the solution delivers order‑of‑magnitude improvements in performance, power consumption, and heat generation for AI, HPC, and database workloads. The platform also embeds intrinsic cybersecurity features that protect distributed servers from advanced threats, making it suitable for secure, on‑premises AI deployments and hybrid‑cloud environments.
Target Audience
Primary customers are server OEMs, national laboratories, and operators of on‑premises data centers—including hyperscalers—who need energy‑efficient, high‑performance compute platforms for AI, HPC, and large‑scale database applications.
Features
- Scale‑out ports on every CPU and accelerator core for low‑latency, high‑throughput inter‑processor communication, bypassing PCIe and legacy interconnect limits
- HRAM intelligent memory subsystem with multiple memory types and hierarchies, removing processor‑level DRAM controllers and improving bandwidth and security
- Server‑on‑a‑Chip integrating compute cores, virtualization hardware, and IOMMU support for fully virtualized, high‑transaction workloads (e.g., web services, in‑memory databases)
- Dedicated Application, Database, and Math processor families with cache‑coherent terabyte‑scale memory and built‑in vector, matrix, tensor, and transform functions
- Intrinsic cybersecurity mechanisms that isolate and protect distributed server nodes against sophisticated cyber‑threats
- Compatibility with both DDR5 DIMMs and HRAM, enabling flexible memory configurations for diverse workloads