SiLogy develops Viv, an AI verification engineer that automates the debugging of test failures in integrated circuits by analyzing log files and code, significantly reducing the time to identify bugs. By enabling chip developers to root-cause issues up to ten times faster, SiLogy enhances productivity and accelerates the design verification process.
Funding
$500K raised to dateRaised to date based on public sources. This may differ from the amount the company actually raised and is based only on what is publicly available on the internet.
Founders
Product
Problem
Debugging test failures in integrated circuits is a time-consuming process, often requiring engineers to manually analyze extensive log files and code. This manual debugging slows down the design verification process and hinders overall productivity.
Solution
SiLogy offers Viv, an AI-powered verification engineer that automates the debugging of test failures in integrated circuits. Viv analyzes log files and code to identify the root cause of bugs, significantly reducing the time required for debugging. By automating repetitive tasks and providing clues about the causes of test failures, Viv enables chip developers to accelerate the design verification process and improve productivity. The platform can be hosted on-premise, ensuring data security.
Target Audience
The primary target audience includes chip developers and verification engineers involved in the design and testing of integrated circuits.
Features
- AI-driven analysis of log files, code, and (soon) waveform files to identify the root cause of test failures.
- Support for multiple simulators, including Synopsys VCS, Siemens QuestaSim, Verilator, and Vivado Simulator.
- On-premise hosting option to ensure data security and compliance.
- Test runner that supports most commercial simulators.
- Suggestions for potential bug locations, citing specific code and waveforms.
- SOC2 certification in progress.